Thermally stable, sub-nanometer equivalent oxide thickness gate stack for gate-first In 0.53 Ga 0.47 As metal-oxide-semiconductor field-effect-transistors

• Published in: Applied physics letters Vol. 100; no. 6; pp. 063505 - 063505-3
• Main Authors: El Kazzi, M., Czornomaz, L., Rossel, C., Gerl, C., Caimi, D., Siegwart, H., Fompeyrine, J., Marchiori, C.
• Format: Journal Article
• Published: Crown 08-02-2012
• ISSN: 0003-6951; 1077-3118
• DOI: 10.1063/1.3683472

Metal-oxide-semiconductor (MOS) capacitors were fabricated by depositing composite 2nm HfO
2
/1nm Al
2
O
3
/1nm a-Si gate stacks on p-In
0.53
Ga
0.47
As/InP (001) substrates. Thanks to the presence of the Al
2
O
3
barrier layer, a minimum amount of the a-Si passivating layer is oxidized during the whole fabrication process. The capacitors exhibit excellent electrical characteristics with scaled equivalent oxide thickness (EOT) of 0.89nm and mid-gap interface state density of 5×10
11
eV
−1
cm
−2
upon post-metallization anneal up to 550°C. Gate-first, self-aligned MOS field-effect-transistors were fabricated with a similar 5nm HfO
2
/1nm Al
2
O
3
/1nm a-Si gate stack and raised source and drain (600°C for 30min). Owing to the excellent thermal stability of the stack, no degradation of the gate stack/semiconductor interface is observed, as demonstrated by the excellent capacitance vs voltage characteristics and the good mobility values (peak at 1030 cm
2
V
−1
s
−1
and 740 cm
2
V
−1
s
−1
at carrier density of 6.5×10
12
cm
−2
) for a 1.3nm EOT.