Two gates are better than one - double-gate MOSFET process

• Published in: IEEE circuits and devices magazine Vol. 19; no. 1; pp. 48 - 62
• Main Authors: Solomon, P M, Guarini, K W, Zhang, Y, Chan, K, Jones, E C, Cohen, G M, Krasnoperova, A, Ronay, M, Dokumaci, O, Hovel, H J, Bucchignano, J J, Cabral, C, Lavoie, C, Ku, V, Boyd, D C, Petrarca, K, Yoon, J H, Babich, I V, Treichler, J
• Format: Journal Article
• Language: English
• Published: 01-01-2003
• ISSN: 8755-3996
• DOI: 10.1109/MCD.2003.1175108

A planar self-aligned double-gate MOSFET process has been implemented where a unique sidewall source/drain structure (S/D) permits self-aligned patterning of the back-gate layer after the S/D structure is in place. This allows coupling the silicon thickness control inherent in a planar, unpatterned layer with VLSI self-alignment techniques and also gives independently controlled front and back gates. The demanding structure led to process innovations primarily in front-end CMP, where planarity within 5 nm was achieved on an 8-in diameter wafer as well as in silicided silicon source/drain sidewalls, with minimal encroachment of the silicide. Double-gate FET (DGFET) operation is demonstrated, with good transport at both interfaces. Dense circuit layouts are achieved with multifinger devices, and logic inverters with back-gate-controlled load current as well as NOR logic using the two gates of a single transistor as inputs are demonstrated.