OC-192 transmitter and receiver in standard 0.18-mum CMOS

• Published in: IEEE journal of solid-state circuits Vol. 37; no. 12; pp. 1768 - 1780
• Main Authors: Cao, J, Green, M, Momtaz, A, Vakilian, K, Chung, D, Jen, Keh-Chee, Caresosa, M, Wang, X, Tan, Wee-Guan, Cai, Yijun, Fujimori, L, Hairapetian, A
• Format: Journal Article
• Language: English
• Published: 01-12-2002
• ISSN: 0018-9200
• DOI: 10.1109/JSSC.2002.804336

This paper presents the first fully integrated SONET OC-192 transmitter and receiver fabricated in a standard 0.18-mum CMOS process. The transmitter consists of an input data register, 16-b-wide first-in-first-out (FIFO) circuit, clock multiplier unit (CMU), and 16:1 multiplexer to give a 10-Gb/s serial output. The receiver integrates an input amplifier for 10-Gb/s data, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. An on-chip LC-type voltage-controlled oscillator (VCO) is employed by both the transmitter and receiver. The chipset operates at multiple data rates (9.95-10.71 Gb/s) with functionality compatible with the multisource agreement (MSA) for 10-Gb transponders. Both chips demonstrate SONET-compliant jitter characteristics. The transmitter 10.66-GHz output clock jitter is 0.065 UI/pp/ (unit interval, peak-to-peak) over a 50-kHz-80-MHz bandwidth. The receiver jitter tolerance is more than 0.4 UI/pp/ at high frequencies (4-80 MHz). A high level of integration and low-power consumption is achieved by using a standard CMOS process. The transmitter and receiver dissipate a total power of 1.32 W at 1.8 V and are packaged in a plastic ball grid array with a footprint of 11x11 mm(2).