Through-Silicon-Via Underfill Dispensing for 3D Die/Interposer Stacking

• Main Author: Le, Fuliang
• Format: Dissertation
• Language: English
• Published: ProQuest Dissertations & Theses 01-01-2014
• Subjects: Aerospace engineering
• ISBN: 9781339172101; 1339172100

The next generation packaging keeps up with the increased demands of functionality by using the third dimension. 3D chip stacking with TSVs has been identified as one of the major technologies to achieve higher silicon density and shorter interconnection. In order to protect solder interconnections from hostile environments and redistribute thermal stress caused by CTE mismatch, underfill should be applied for the under-chip spaces. In this study, TSV underfill dispensing is introduced to address the underfill challenge for 3D chip stacks. The material properties are first measured and the general trend indicates viscosity and contact angle dropping significantly with an increase in temperature, and surface tension falling slightly as the temperature increases. Underfill should assure a complete encapsulation, avoiding excessive filling time that can result in substantial manufacturing delays. Typically, the inflows for TSV underfill can be free droplets or a constant flow rate. For a constant inflow, the underfill flow is driven by pressure difference and the filling time is governed by flow radius, gap clearance and the constant flow rate. For an inflow of free droplets, the underfill flow is driven by capillary action and the filling time is related to viscosity, flow radius, gap clearance, surface tension, contact angle and TSV size. In general, TSV underfill dispensing with a constant inflow has much shorter filling time than dispensing with an inflow of free droplets. TSV underfill dispensing on a 3D chip stack may induce the risk of an edge flood failure. In order to avoid an edge flood, fluid pressure around the sidewalls of a 3D chip stack cannot exceed limit equilibrium pressure. For TSV dispensing with free droplets, there is no risk of forming an edge flood. However, for a constant inflow, TSV dispensing should be carefully controlled to avoid excessive pressure. Besides, it is suggested that the TSVs in stacked chips be aligned in the vertical direction because this aligned configuration has the lowest risk to form an edge flood. In order to find a trade-off between short filling time and low risk of an edge flood, an optimized TSV pattern, including central/outer TSVs, is proposed for the underfill of a 3D chip stack. The central TSVs are set for a constant inflow to obtain a fast filling effect. The outer TSVs are set for free droplets to eliminate the potential edge flood during underfilling the area around the chip edges. The test vehicle for the underfill test is a four-layer die/interposer stack. In each layer, two flip chips are mounted beneath an interposer. The vertical-aligned configuration and the optimized TSV pattern are used in the test vehicle. In the underfill dispensing process, I-Pass edge dispensing is still used to fill the gaps beneath the bottom two layers. Afterwards, a constant inflow is dispensed into the central TSVs until the underfill flow reaches the chip edges. The remaining unfilled area is completed by dispensing free droplets into the outer TSVs. The underfill effect is inspected by acoustic scanning and cross-sections. Inspection results show that the underfill is completed without voids and the solder joints are well covered by an encapsulant. In addition, compared with other prevailing underfill methods, the fillet occupies less space on a substrate, leading to a rise in silicon packaging density.