A general BIST-amenable method of test generation for iterative logic arrays

• Published in: Proceedings 18th IEEE VLSI Test Symposium pp. 171 - 176
• Main Authors: Boateng, I.O., Takahashi, H., Takamatsu, Y.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2000
• Subjects: Iterative methods; Logic arrays; Logic testing
• ISBN: 9780769506135; 0769506135
• ISSN: 1093-0167; 2375-1053
• DOI: 10.1109/VTEST.2000.843842

In this work, we call a set of a constant number of test patterns that have a fixed fault coverage for any size of a given ILA a fixed coverage fixed size test set (FixCoST). In this paper, we first show the existence of FixCoSTs, each test pattern of which is applied to the rows and columns of the array under test, as binary patterns that are repetitions of a few cell-input patterns. Such FixCoSTs can be applied in a BIST framework. Next, we devise a means and formulate measures to evaluate the individual repetitive test patterns of such a FixCoST and the FixCoST as a set. Then, we exploit the repetitive nature of the constituent test patterns of the FixCoSTs to develop a BIST-amenable method for generating FixCoSTs that apply all permutations of binary patterns to each cell of the ILA under test.