Testability expertise and test planning from high-level specifications

• Published in: Proceedings. 'Meeting the Tests of Time'., International Test Conference pp. 692 - 699
• Main Authors: Crastes de Paulet, M., Karam, M., Saucier, G.
• Format: Conference Proceeding
• Language: English
• Published: IEEE Comput. Soc. Press 1989
• Subjects: Arithmetic; Artificial intelligence; Controllability; Hardware; Logic testing; Multiplexing; Observability; Read-write memory; Registers; Skeleton
• DOI: 10.1109/TEST.1989.82357

The testability expertise of boards and ASICs (application-specific integrated circuits) relies on high-level models in the Prolog language. This high-level modeling makes it possible to describe chip and board functions at an adequate level of accuracy without giving useless details. Each chip is successfully considered as a test goal; difficult chips are identified. Design modifications in terms of multiplexers or scan path insertion are proposed according to a test strategy. As a final result of this analysis, the test planning (test data flow and test control, test scheduling) is defined. The resulting test program skeleton is then formatted to lead to the final test program.< >