Accurate evaluation of gate delay for low-power and high-density 0.18 /spl mu/m CMOSFET technology

• Published in: ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) pp. 427 - 429
• Main Authors: Myoung-Kyu Park, Hi-Deok Lee, Myhoung-Jun Jang, Jung-Hun Choi, Dae-Gwan Kang, Jeong-Mo Hwang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1999
• Subjects: Capacitance; CMOS technology; CMOSFETs; Delay effects; MOS devices; MOSFET circuits; Random access memory; Ring oscillators; Silicon; Threshold voltage
• ISBN: 0780357272; 9780780357273
• DOI: 10.1109/ICVC.1999.820953

The gate delay of ring oscillators in high V/sub T/ CMOSFET technology is characterized with respect to various channel widths (0.72 /spl mu/m-10 /spl mu/m). An expression for gate delay including the channel-width independent capacitance components is derived and compared with experimental results. Substantial increase of gate delay in the narrow channel width region is found due to channel width independent capacitance components which are inherent to transistors. Although the channel width independent capacitance is negligible in wide channel width, gate delay of narrow channel width (/spl les/1 /spl mu/m) ring oscillator increased more than 20% compared with 5 /spl mu/m channel width ring oscillator.