6.7 A 1.2e− temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA

• Published in: 2016 IEEE International Solid-State Circuits Conference (ISSCC) pp. 122 - 123
• Main Authors: Shiraishi, Kei, Shinozuka, Yasuhiro, Yamashita, Tomonori, Sugiura, Kazuhide, Watanabe, Naoto, Okamoto, Ryuta, Ashitani, Tatsuji, Furuta, Masanori, Itakura, Tetsuro
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-01-2016
• Subjects: CMOS image sensors; Electronics packaging; Noise measurement; Power demand; Solid state circuits; Switches; Timing
• ISBN: 1467394661; 9781467394666
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC.2016.7417937

This paper presents a 1.2e-, 3D-stacked CMOS image sensor (CIS) for mobile applications. A key motivation for using a stacked configuration is to minimize the chip area. Also, since numerous components must be integrated into the bottom chip, a scaled 65nm CMOS process is adopted for the bottom chip. The developed CIS features 1.2e- temporal noise with extremely high power efficiency by employing a multiple-sampling (MS) technique. A 2nd-order incremental ΔΣ ADC with inverter-based switched-capacitor integrator realizes the MS technique with low power [1]. However, an exponential number of samples are required to reduce the quantization noise, and conversion speed worsens with higher bit resolution. An extended counting ADC, which is a blend of folding integration and cyclic ADC, attains high resolution with reduced conversion time [2-3]. However, an op-amp with high open-loop gain is required for good linearity and column-to-column matching characteristics, which increases power consumption. Also it is not suitable for scaled CMOS technology. An alternative approach is a single-slope (SS) based MS technique [4], in which two SS-ADCs convert the same pixel signal, and the readout signal is averaged in the digital domain, but the noise improvement is limited to -3dB and the power consumption and area occupation are roughly doubled.