Poster: Toward Operating System Assisted Hierarchical Memory Management for Heterogeneous Architectures

• Published in: 2012 SC Companion: High Performance Computing, Networking Storage and Analysis p. 1352
• Main Authors: Gerofi, Balazs, Hori, Atsushi, Shimada, Akio, Ishikawa, Yutaka
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-11-2012
• Subjects: coprocessor; manycore; memory management; operating systems
• ISBN: 1467362182; 9781467362184
• DOI: 10.1109/SC.Companion.2012.182

The Intel Many Integrated Core (Intel MIC) architecture is Intel's latest design targeted for processing highly parallel workloads. The Intel MIC architecture is implemented on a PCI card, and has its own on-board memory, connected to the host memory through PCI DMA operations. The on-board memory is faster than the one in the host, but it is significantly smaller, requiring the programmer to partition larger computational problems into smaller pieces that can run on a co-processor. However, the Intel MIC architecture features a standard memory management unit (MMU), where the operating system keeps track of the physical memory and manages the mapping from virtual to physical addresses. Thus, the OS running on the many-core unit can transparently move data between the card and the host, similarly how swapping is performed to disk in traditional operating systems. Essentially, the co-processor's memory behaves as another level in the memory hierarchy.