A simple algorithm for fanout optimization using high-performance buffer libraries

A simple algorithm for fanout optimization using high-performance buffer libraries

We present an algorithm for computing minimal-area fanout networks satisfying a delay constraint. We focus on one type of fanout network structure, the fanout chain. We show that, when using libraries designed for high-speed custom CMOS chips, the fanout chain typically produces minimal-area fanout...

Full description

Saved in:
Bibliographic Details
Published in:Proceedings of 1993 International Conference on Computer Aided Design (ICCAD) pp. 466 - 471
Main Authors: Kodandapani, K., Grodstein, J., Domic, A., Touati, H.
Format: Conference Proceeding
Language:English
Published: IEEE 1993
Subjects:
Circuit synthesis
CMOS logic circuits
CMOS technology
Computer networks
Delay
Inverters
Logic design
Software libraries
Space technology
Topology
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:We present an algorithm for computing minimal-area fanout networks satisfying a delay constraint. We focus on one type of fanout network structure, the fanout chain. We show that, when using libraries designed for high-speed custom CMOS chips, the fanout chain typically produces minimal-area fanout networks for a given delay constraint. We then present fast, near-optimal algorithms to compute these fanout structures.
ISBN:9780818644900
0818644907
DOI:10.1109/ICCAD.1993.580099