A 2.17 mm2 125 mW reconfigurable SVD chip for IEEE 802.11n system

• Published in: 2010 Proceedings of ESSCIRC pp. 534 - 537
• Main Authors: Chen, Yen-Liang, Jheng, Ting-Jyun, Zhan, Cheng-Zhou, Wu, An-Yeu
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-09-2010
• Subjects: Engines; Frequency measurement; IEEE 802.11n Standard; MIMO; Receiving antennas; Wireless LAN
• ISBN: 9781424466627; 1424466628
• ISSN: 1930-8833; 2643-1319
• DOI: 10.1109/ESSCIRC.2010.5619761

This paper presents a reconfigurable singular value decomposition (SVD) engine design for the IEEE 802.11n applications. This engine can support all antenna modes in an 802.11n system. The proposed design techniques can reduce decomposing latency, enhance hardware utilization, and increase system throughput. The proposed reconfigurable SVD engine design is implemented and fabricated in UMC 90 nm 1P9M CMOS technology. The maximum operating frequency is measured 101.2 MHz and the corresponding power dissipation is 125 mW. The core size is 2.17 mm 2 and the die size occupies 4.93 mm 2 .