Substrate bias effects on short channel length and narrow channel width PMOS devices at cryogenic temperatures

• Published in: Proceedings of the Workshop on Low Temperature Semiconductor Electronics pp. 53 - 57
• Main Authors: Deen, M.J., Wang, J., Yan, Z.X., Zuo, Z.P.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1989
• Subjects: Cryogenics; Degradation; Doping; Integrated circuit interconnections; MOS devices; Rough surfaces; Surface resistance; Surface roughness; Tellurium; Temperature
• DOI: 10.1109/LTSE.1989.50181

The effects of substrate biasing on the characteristics of PMOS devices with varying channel lengths and widths were studied as a function of temperature from 300 K to 77 K. Results on the low field intrinsic mobility, the mobility surface and substrate bias degradation constants, and the effective low field mobility are discussed. The variation of the peak substrate current normalized to the drain current and of drain-induced-barrier-lowering with substrate bias for both groups of devices is also presented and discussed.< >