A 32-Bit RISC Implemented in Enhancement-Mode JFET GaAs

A 32-Bit RISC Implemented in Enhancement-Mode JFET GaAs

This paper describes the design of a 32-bit reduced instruction set computer (RISC) implemented in Gallium Arsenide using enhancementmode junction field effect transistors. The microprocessor chip is designed to implement the Stanford MIPS architecture using a four stage pipe. The chip contains 22 r...

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Bibliographic Details
Published in:MILCOM 1986 - IEEE Military Communications Conference: Communications-Computers: Teamed for the 90's Vol. 3; pp. 37.3.1 - 37.3.5
Main Authors: Rasset, T.L., Niederland, R.A., Lane, J.H., Geideman, W.A.
Format: Conference Proceeding
Language:English
Published: IEEE 01-10-1986
Subjects:
CMOS logic circuits
FETs
Gallium arsenide
Integrated circuit technology
Inverters
Logic devices
Microprocessors
Reduced instruction set computing
Silicon
Switches
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Summary:This paper describes the design of a 32-bit reduced instruction set computer (RISC) implemented in Gallium Arsenide using enhancementmode junction field effect transistors. The microprocessor chip is designed to implement the Stanford MIPS architecture using a four stage pipe. The chip contains 22 registers, a full barrel shifter, a 32-bit ALU and necessary control circuits. The processor is expected to operate with an average throughput rate in excess of 100 million instructions per second.
DOI:10.1109/MILCOM.1986.4805825