Design techniques and performance of an LSI-based 2B1Q transceiver

Design techniques and performance of an LSI-based 2B1Q transceiver

Examines a 2B1Q transceiver system which was selected as the standard for an ISDN (integrated services digital network) loop transmission systems in the US. An LSI-based 2B1Q transceiver consisting of three LSI chips has been developed. Echo tail suppression, receiver design to configure stable deci...

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Bibliographic Details
Published in:IEEE Global Telecommunications Conference and Exhibition. Communications for the Information Age pp. 778 - 782 vol.2
Main Authors: Arai, M., Yamaguchi, M., Nakagawa, F., Shibata, H., Kanemasa, A., Makabe, T., Koike, S.
Format: Conference Proceeding
Language:English
Published: IEEE 1988
Subjects:
Circuits
Decision feedback equalizers
Echo cancellers
Finite impulse response filter
IIR filters
ISDN
Large scale integration
Tail
Timing
Transceivers
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Summary:Examines a 2B1Q transceiver system which was selected as the standard for an ISDN (integrated services digital network) loop transmission systems in the US. An LSI-based 2B1Q transceiver consisting of three LSI chips has been developed. Echo tail suppression, receiver design to configure stable decision feedback equalizer (DFE) operation and to improve NEXT performance, and the accurate analog front end circuit are discussed. Experimental results show that satisfactory performance is obtained.< >
DOI:10.1109/GLOCOM.1988.25944