C-testable systolic arrays

• Published in: [1993] Proceedings Third Great Lakes Symposium on VLSI-Design Automation of High Performance VLSI Systems pp. 22 - 26
• Main Author: Faroughi, N.
• Format: Conference Proceeding
• Language: English
• Published: IEEE Comput. Soc. Press 1993
• Subjects: Circuit faults; Circuit testing; Computer science; Integrated circuit interconnections; Pipelines; Systolic arrays
• ISBN: 9780818634307; 0818634308
• DOI: 10.1109/GLSV.1993.224488

A reconfigurable cell model for C-testability of systolic arrays is presented. With this model each systolic array is reconfigurable to a set of C-testable orthogonal iterative systolic arrays (OISAs). The time complexity of a systolic array is determined from the time complexity of its corresponding OISAs. The C-testable time complexities of some known systolic arrays are presented.< >