VLSI implementation of a 1616 DCT

VLSI implementation of a 1616 DCT

The implementation of a 16*16 discrete cosine transform (DCT) chip using a concurrent architecture is presented. The chip is designed for real-time processing of 14.3 MHz sampled video data. The architecture and accuracy studies for finite-wordlength processing are discussed. The chip was implemente...

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Bibliographic Details
Published in:ICASSP-88., International Conference on Acoustics, Speech, and Signal Processing pp. 1973 - 1976 vol.4
Main Authors: Chen, T.C., Sun, M.T., Gottlieb, A.M.
Format: Conference Proceeding
Language:English
Published: IEEE 1988
Subjects:
Arithmetic
Circuit synthesis
Computer architecture
Discrete cosine transforms
Discrete transforms
Matrix decomposition
Registers
Routing
Sun
Very large scale integration
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Summary:The implementation of a 16*16 discrete cosine transform (DCT) chip using a concurrent architecture is presented. The chip is designed for real-time processing of 14.3 MHz sampled video data. The architecture and accuracy studies for finite-wordlength processing are discussed. The chip was implemented, tested, and found to be fully functional. Possible variations are presented for multipurpose (variable transform sizes, forward-backward transform) applications.< >
ISSN:1520-6149
2379-190X
DOI:10.1109/ICASSP.1988.197011