A single-chip speech recognition system with embedded flash memory and configurable data path

• Published in: Proceedings of the 28th European Solid-State Circuits Conference pp. 327 - 330
• Main Authors: Cali, L., Lertora, F., Borgatti, M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2002
• Subjects: CMOS technology; Control systems; Coprocessors; Embedded system; Engines; Flash memory; Memory architecture; Speech recognition; System-on-a-chip; User interfaces

The design of a single-chip, processor-based system with embedded built-in speech recognition capabilities is presented. The proposed system-on-chip is intended to be used for the implementation of autonomous embedded systems featuring voice control capabilities and command-oriented user interface. To allow a good flexibility of the recognition system and to achieve a single-chip system implementation, the main processing functionalities have been organized as co-processors and integrated around a 32-bit processor and a 2Mb embedded flash memory. The architecture of the system that features a recognition engine with a configurable data path is discussed. The silicon area required by the system is 25 mm 2 in a 0.18µm CMOS embedded flash technology.