GF(2/sup K/) multipliers based on Montgomery Multiplication Algorithm

• Published in: 2004 IEEE International Symposium on Circuits and Systems (ISCAS) Vol. 2; pp. II - 849
• Main Authors: Fournaris, A.P., Koufopavlou, O.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2004
• Subjects: Arithmetic; Cryptography; Equations; Galois fields; Hardware; Inspection; Logic gates; Polynomials; Very large scale integration
• ISBN: 078038251X; 9780780382510
• DOI: 10.1109/ISCAS.2004.1329405

Finite Field arithmetic is becoming increasingly a very prominent solution for calculations in many applications. The most demanding Finite Field arithmetic operation is multiplication. In this paper two Finite Field multiplier architectures and VLSI implementations are proposed using the Montgomery Multiplication Algorithm. The first architecture (Folded) is optimized in order to minimize the silicon covered area (gate count) and the second (Pipelined) is optimized in order to reduce the multiplication time delay. Both architectures are measured in terms of gate count-chip covered area and multiplication time delay and have more than adequate results in comparison with other known multipliers.