Layout synthesis of MOS digital cells

Layout synthesis of MOS digital cells

The main issues specific to the cell generation of MOS digital circuits are reviewed. The discussion concentrates on the direct use of arbitrary cells, or the quick generation of new library items, rather than the application of general place and route algorithms. Specifically, transistor ordering f...

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Bibliographic Details
Published in:27th ACM/IEEE Design Automation Conference pp. 241 - 245
Main Author: Domic, A.
Format: Conference Proceeding
Language:English
Published: IEEE 1990
Subjects:
Assembly
Circuit synthesis
CMOS technology
Compaction
Digital circuits
Logic
MOSFETs
Read only memory
Software libraries
Solid modeling
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Summary:The main issues specific to the cell generation of MOS digital circuits are reviewed. The discussion concentrates on the direct use of arbitrary cells, or the quick generation of new library items, rather than the application of general place and route algorithms. Specifically, transistor ordering for Boolean gates, routing a cell, and polygon generation are discussed.< >
ISBN:0897913639
9780897913638
ISSN:0738-100X
DOI:10.1109/DAC.1990.114861