On the Output Conductance Dispersion due to Traps and Self-Heating in Large Bulk, FDSOI and FinFET nMOS Devices

• Published in: 2024 IEEE European Solid-State Electronics Research Conference (ESSERC) pp. 345 - 348
• Main Authors: Tondelli, L., Scholten, A. J., Asanovski, R., Pijper, R. M. T., Dinh, T. V., Selmi, L.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 09-09-2024
• Subjects: Bulk FinFET; Bulk MOSFET; Dielectrics; Dispersion; FDSOI MOSFET; FinFETs; Logic gates; Performance evaluation; Self-Heating; Silicon-on-insulator; Temperature; Temperature sensors; Thermal resistance; Traps; Voltage
• ISSN: 2643-1319
• DOI: 10.1109/ESSERC62670.2024.10719502

We report experimental investigations on the AC small signal output conductance (g_{D D}) of large nMOSFETs with bulk, FDSOI, and bulk FinFET architecture. The g_{D D} frequency spectra reveal opposite trends at low and high gate voltage \mathrm{V}_{\mathrm{GS}}. Furthermore, an unexpected anomaly is observed at \mathrm{V}_{\mathrm{GS}} close to the value where the sensitivity to temperature of the DC IV transfer characteristics changes sign.Self-heating is scrutinized as a possible unique origin of the \mathrm{g}_{\mathrm{DD}} dispersion. An additional non-negligible role of trap states is put in evidence by numerical simulations taking self-consistently into account electrothermal effects and the possible presence of gate dielectric traps.The results can reduce inaccuracies in determining the thermal resistances from the g_{D D} frequency dispersion data, and support better design of large FETs and circuits for RF applications.