New Resource Efficient Multi-PUF Techniques

• Published in: 2024 IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS) pp. 469 - 473
• Main Authors: Bonagiri, Sai Preetham, S. Khalid, Mohammed A.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 11-08-2024
• Subjects: Adaptation models; Complexity theory; hardware-based security; Linear regression; Machine learning; Measurement; Memory management; Physical unclonable function; Public Unclonable Functions (PUFs)
• ISSN: 1558-3899
• DOI: 10.1109/MWSCAS60917.2024.10658776

The Physical Unclonable Function (PUF) is a lightweight hardware solution that offers affordable hardware-based security for electronic devices and systems. Due to their unpredictable response generation and inability to be replicated, their utilization is rapidly growing in authentication and security applications. It presents an alternative to conventional cryptographic systems that require large chip area and memory storage. However, a significant concern lies in the vulnerability of PUFs to popular machine learning attacks, such as Covariance Matrix Adaptability and Evaluation Strategy (CMA-ES) attacks and Linear Regression (LR) attacks, among others. To mitigate these vulnerabilities, numerous PUF models have been proposed, aiming to make it difficult to determine the Challenge-Response Pairs (CRPs) for those PUFs. Among these models, Multi-PUFs (MPUFs) have gained popularity for their success in enhancing security. however, MPUFs demand considerable resources and exhibit relatively low PUF metric values, despite their improved security against ML attacks. To increase resource efficiency further, two new Multi-PUF technique has been proposed in this paper, aiming to achieve a balance between resource utilization and challenge obfuscation complexity. The key idea involves reducing the number of resources used in a PUF line while concurrently increasing complexity during challenge obfuscation. The proposed design is implemented and verified on the Arty A7 100t FPGA board using AMD Vivado and Vitis Environment. Experimental results show that resource usage has been significantly reduced, by 9 and 46.5 percent respectively, for the two proposed techniques.