Phase-locked loop with DCoffset removal for single-phase grid-connected converters

• Published in: Electric power systems research Vol. 194
• Main Authors: Smadi, Issam A., Bany Fawaz, Bayan H.
• Format: Journal Article
• Language: English
• Published: Elsevier B.V 01-05-2021
• Subjects: Dc-offset rejection; Delay signal cancellation; Grid synchronization; Grid-tied converters; Phase-locked loop; Small-signal model; Variable-length time delay; Dc-offset rejection; Delay signal cancellation; Variable-length time delay; Phase-locked loop; Small-signal model; Grid-tied converters; Grid synchronization
• ISSN: 0378-7796; 1873-2046
• DOI: 10.1016/j.epsr.2020.106980

•A simple method to remove the effect of the DC-offset in the grid synchronization process is proposed.•The proposed PLL relies on a delay signal cancellation operator that is not restricted to a specific time delay.•The proposed PLL has flexibility and an advantage over the other PLLs.•The small-signal model of the proposed PLL is derived for stability analysis and loop filter design.•The proposed PLL has the fastest dynamic response, with minimum settling time compared to other PLLs.
DC-offset in the input of the phase-locked loop (PLL) is an emerging problem that causes oscillations in the estimated fundamental grid phase, frequency, and voltage amplitude. The DC-offset rejection in grid synchronization is a difficult task due to its low-frequency nature. This paper proposes a method to remove the DC-offset in the single-phase grid synchronization utilizing delay signal cancellation (DSC) and a variable-length time delay (VLTD) based PLL. The small-signal model, stability analysis, and controller gains selection are discussed. The proposed PLL is compared with other single-phase PLLs in terms of the phase settling time, the phase percent maximum overshoot, and the peak of the estimated frequency, to show its advantages.