Delay fault testing for VLSI circuits

• Main Author: Krstic, Angela
• Format: Dissertation
• Language: English
• Subjects: engineering, electronics and electrical
• ISBN: 9780599208056; 0599208058

With the ever increasing speed of integrated circuits, violations of the performance specifications are becoming a major factor affecting the product quality level. The need for testing timing defects is expected to grow further with the current design trends of moving towards deeper submicron devices. This dissertation proposes several new techniques for delay fault test generation, design for delay fault testability and delay test application.
Functional sensitizable (FS) path delay faults represent faults that can affect the performance of the design but they are often ignored for testing. This is because testing FS paths requires considering multiple path delay faults. Most circuits have a large fraction of these faults. An FS path can be tested with many different tests. The quality of these tests varies depending on their ability to detect the target fault. We present two techniques for testing FS paths. The first technique focuses on generating a small number of high quality functional sensitizable tests for each target path. To find tests that have a high probability of detecting the fault, we use the timing information in the test generation process. This technique cannot guarantee detection of the fault. The second technique concentrates on generating tests that can guarantee the detection of an FS fault. Our goal is to identify and test a minimum set of multiple path delay faults that contain the target path and that can affect the performance of the circuit. These multiple path delay faults belong to a class of primitive faults. Identification and testing of all primitive faults is a complex problem. We present a complete algorithm for testing primitive faults consisting of two paths.
To ensure that the circuit is delay fault-free, all primitive faults of all cardinalities have to be identified and tested. For large circuits, deriving tests for primitive faults of cardinality higher than two is impractical. We propose a design for testability method that eliminates the need to test primitive faults containing more than two paths. Our technique is based on iterative test point insertion such that we can guarantee that the circuit is delay fault-free by testing only primitive faults consisting of up to two paths.
Some path delay faults do not have to be targeted for delay test generation. We present a technique for identifying such faults in non-scan sequential circuits. These faults include untestable faults and paths that cannot independently determine the performance. Identifying the set of paths that do not have to be tested can result in reduced test generation effort and smaller test set.
Path delay fault model is most adequate for detecting small, distributed timing defects that can occur as a result of manufacturing process variations. One of the main problems in path delay fault testing is the extremely large number of faults in practical designs. To alleviate this problem, we propose a resynthesis technique for path count reduction. Our method employs an ATPG-based logic optimization technique and results in circuits with significant reduction in the number of faults.
Testing delay defects requires application of test vectors at the rated speed of the circuit. Due to high cost of fast testers, it is not unusual that testers used in test facilities are slower than the new designs. We propose a novel at-speed delay testing scheme that allows the use of slow testers for testing fast devices.