Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor

• Published in: Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture pp. 123 - 133
• Main Authors: Gibert, Enric, Sánchez, Jesús, González, Antonio
• Format: Conference Proceeding
• Language: English
• Published: Los Alamitos, CA, USA IEEE Computer Society Press 18-11-2002
• Series: ACM Conferences
• Subjects: Computer systems organization > Architectures > Parallel architectures > Very long instruction word; Computer systems organization > Architectures > Serial architectures > Complex instruction set computing; Computer systems organization > Architectures > Serial architectures > Reduced instruction set computing; Hardware > Integrated circuits > Semiconductor memory > Dynamic memory; Software and its engineering > Software organization and properties > Contextual software domains > Operating systems > Process management > Scheduling
• ISBN: 0769518591; 9780769518596
• DOI: 10.5555/774861.774875

Clustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully-distributed architectures, where the register file, the functional units and the data cache are partitioned, are particularly effective to deal with these constraints and besides they are very scalable. In this paper effective instruction scheduling techniques for a clustered VLIW processor with a word-interleaved cache are proposed. Such scheduling techniques rely on: (i) loop unrolling and variable alignment to increase the percentage of local accesses, (ii) a latency assignment process to schedule memory operations with an appropriate latency and (iii) different heuristics to assign instructions to clusters. In particular, the number of local accesses is increased by more than 25% if these techniques are used and the ratio of stall time over compute time is small.Next, the main source of remote accesses and stall time is investigated. Stall time is mainly due to remote hits, and Attraction Buffers are used to increase local accesses and reduce stall time. Stall time is reduced by 29% and 34% depending on the scheduling heuristic. IPC results for a word-interleaved cache clustered VLIW processor are similar to those of the multiVLIW (a cache-coherent clustered processor with a more complex hardware design), and are 10% and 5% better (depending on the scheduling heuristic) than the lPC for a clustered processor with a unified cache.