Interactive presentation: Implementation of AES/Rijndael on a dynamically reconfigurable architecture
Reconfigurable architectures provide the user the capability to couple performance typical of hardware design with the flexibility of the software. In this paper, we present the design of AES/Rijndael on a dynamically reconfigurable architecture. We will show a performance improvement of three order...
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Published in: | Proceedings of the conference on Design, automation and test in Europe pp. 355 - 360 |
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Main Authors: | , , , |
Format: | Conference Proceeding |
Language: | English |
Published: |
San Jose, CA, USA
EDA Consortium
16-04-2007
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Series: | ACM Conferences |
Subjects: | |
Online Access: | Get full text |
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Summary: | Reconfigurable architectures provide the user the capability to couple performance typical of hardware design with the flexibility of the software. In this paper, we present the design of AES/Rijndael on a dynamically reconfigurable architecture. We will show a performance improvement of three order of magnitude compared to the reference code and up to 24x speed-up figure wrt fast C implementations over a RISC processor. A maximum throughput of 546 Mbit/sec is achieved. Compared to prior art, we show better energy efficiency with respect to the other programmable solutions, obtaining up to 3 Mbit/sec/mW. |
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ISBN: | 9783981080124 3981080122 |
DOI: | 10.5555/1266366.1266441 |