A 35-mW 3.6-mm(2) fully integrated 0.18-mum CMOS GPS radio

• Published in: IEEE journal of solid-state circuits Vol. 38; no. 7; pp. 1163 - 1171
• Main Authors: Montagna, G, Gramegna, G, Bietti, I, Franciotta, M, Baschirotto, A, De Vita, P, Pelleriti, R, Paparo, M, Castello, R
• Format: Journal Article
• Language: English
• Published: 01-07-2003
• ISSN: 0018-9200
• DOI: 10.1109/JSSC.2003.813298

A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network and one external reference for the synthesizer. The receiver downconverts the GPS L1 signal at 1575.42 MHz to an IF of 9.45 MHz. The complete front-end and frequency synthesizer section have been integrated: low noise amplifier, image rejection mixer, IF active filter, and the full phase-locked loop synthesizer, including voltage-controlled oscillator and loop filter. The front-end measured performances are 81-dB maximum gain, 5.3-dB noise figure, and > 30-dB image rejection. The synthesizer features a phase noise of -95 dBc/Hz at 1-MHz offset and a total integrated phase noise of less than 7 deg rms in the 500-Hz-1.5-MHz band. The front-end and the synthesizer draw, respectively, 11 and 9 mA from a 1.8-V supply. The architecture of the front-end and synthesizer has been geared to high level of integration and reduction of silicon area at the lowest possible power consumption. Consequently, the one reported here is the smallest and most integrated CMOS GPS receiver reported so far.