Through Silicon Via technology using tungsten metallization

• Published in: 2011 IEEE International Conference on IC Design & Technology pp. 1 - 4
• Main Authors: Pares, G, Bresson, N, Minoret, S, Lapras, V, Brianceau, P, Lugand, J F, Anciant, R, Sillon, N
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-05-2011
• Subjects: 3D integration; Copper; DRIE; Filling; SACVD; Silicon; Three dimensional displays; Through-silicon vias; TSV; Tungsten; Via-mid
• ISBN: 1424490197; 9781424490196
• ISSN: 2381-3555; 2691-0462
• DOI: 10.1109/ICICDT.2011.5783204

Through Silicon Vias (TSV) is a very promising technology in advanced packaging, for the replacement of wire bonding. This technology is becoming mandatory for fully integrated products such as SiP, SoP, 3D components integration (e.g memory stacking), or MEMS structure packaging. Different alternatives are currently investigated such as via-first or via-last. Into the via-first family two different approaches can be considered. The TSV's can be done before the FEOL (pre-process approach) or in-between the FEOL and the BEOL (mid process approach). Each solution has advantages and drawbacks depending on the final application in particular. In a first part of this paper the tungsten mid-process TSV technology will be presented and briefly compared to the copper mid-process approaches. Then, the process of the tungsten TSV fabrication will be detailed and morphological characterizations will be presented. We will focus on two specific parts of the process which have been specifically optimized for the tungsten TSV technology: the low temperature insulation oxide and the tungsten deposition-etch back sequence to fill the vias. The results of those optimizations will be presented and discussed. Last, we will introduce the electrical test vehicle used in this work and present the main results regarding via resistances. Some specific recommendations will by proposed in term of design and integration rules in relation with the process constraints.