Microthreading as a Novel Method for Close Coupling of Custom Hardware Accelerators to SVP Processors

• Published in: 2011 14th Euromicro Conference on Digital System Design pp. 525 - 532
• Main Authors: Sykora, J., Kafka, L., Danek, M., Kohout, L.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-08-2011
• Subjects: Computer architecture; Custom accelerators; Hardware; Hardware families of threads; Instruction sets; Message systems; Microthreading; Registers; SVP concurrency model; UTLEON3 processor
• ISBN: 145771048X; 9781457710483
• DOI: 10.1109/DSD.2011.73

We present a new low-level interfacing scheme for connecting custom accelerators to processors that tolerates latencies that usually occur when accessing hardware accelerators from software. The scheme is based on the Self-adaptive Virtual Processor (SVP) architecture and on the micro-threading concept. Our presentation is based on a sample implementation of the SVP architecture in an extended version of the LEON3 processor called UTLEON3. The SVP concurrency paradigm makes data dependencies explicit in the dynamic tree of threads. This enables a system to execute threads concurrently in different processor cores. Previous SVP work presumed the cores are homogeneous, for example an array of micro threaded processors sharing a dynamic pool of micro threads. In this work we propose a heterogeneous system of general-purpose processor cores and custom hardware accelerators. The accelerators dynamically pick families of threads from the pool and execute them concurrently. We introduce the Thread Mapping Table (TMT) hardware unit that couples the software and hardware implementations of the user computations. The TMT unit allows to realize the coupling scheme seamlessly without modifications of the processor ISA. The advantage of the described scheme is in decoupling application programming from specific details of the hardware accelerator architecture (identical behaviour of a software create and hardware create), and in eliminating the influence of hardware access latencies. Our simulation and FPGA implementation results prove that the additional hardware access latencies in the processor are tolerated by the SVP architecture.