FPGA implementation of multilayer feed forward neural network architecture using VHDL

• Published in: 2012 International Conference on Computing, Communication and Applications pp. 1 - 6
• Main Authors: Hariprasath, S., Prabakar, T. N.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-02-2012
• Subjects: Adders; Artificial neural networks; Biological neural networks; Feeds; Field programmable gate arrays; Field-programmable gate array (FPGA); Hardware; hardware implementation; neural networks (NNs); Neurons; VHDL
• ISBN: 1467302708; 9781467302708
• ISSN: 2325-6001
• DOI: 10.1109/ICCCA.2012.6179225

This paper presents a hardware implementation of multilayer feed forward neural networks (FFNN) using Field Programmable gate arrays (FPGAs). In spite of huge improvements in FPGA densities, the number of multipliers in a NN limits the size of the network that can be implemented using a single FPGA and the NN applications are not made commercially viable. The proposed implementation is aimed at reducing the resource requirements, without much compromise on the speed, so that a larger NN can be realized on a single chip at a lower cost. The parallel processing of the layers in an NN has been exploited in this paper to implement larger NNs. An efficient and fast carry look-ahead adder and Booth multiplier are the essential building blocks of the processing elements to perform parallel computation in the neural network. The activation function is implemented using piecewise linear approximation. In this work, a 2-2-1 multilayer feed forward neural network is implemented with different fixed point representation. The hardware resources consumed and the results obtained are presented.