A 21.7-to-27.8GHz 2.6-degrees-rms 40Mw frequency synthesizer in 45nm CMOS for mm-Wave communication applications

• Published in: 2011 IEEE International Solid-State Circuits Conference pp. 278 - 280
• Main Authors: Osorio, J F, Vaucher, C S, Huff, B, v.d. Heijden, Edwin, de Graauw, A
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-02-2011
• Subjects: CMOS integrated circuits; Frequency conversion; Frequency synthesizers; Phase locked loops; Phase noise; Tuning; Voltage-controlled oscillators
• ISBN: 9781612843032; 1612843034
• ISSN: 0193-6530; 2376-8606
• DOI: 10.1109/ISSCC.2011.5746317

This work presents a 21.7-to-27.8GHz frequency synthesizer in a 45nm CMOS process that combines a tuning range of 24.8%, a residual phase modulation of 2.57°rms (with integrated phase noise from 100kHz to 100MHz), and a total power dissipation of 40mW. Combined with a frequency multiplier-by-two circuit and a divider-by-two circuit in a sliding-IF configuration, the PLL provides the four source frequencies required by the IEEE 802.15.3c 60GHz communication standard. In addition, the attained phase noise makes it suitable for microwave links with higher-order modulation schemes used as the back-bone for 3G/LTE base-station networks.