Characterization and modeling of three CMOS diode structures in the CDM to HBM timeframe

Characterization and modeling of three CMOS diode structures in the CDM to HBM timeframe

We present advanced TLP measurement techniques down to 1.2ns pulses. We compare gated, STI and abutted tie diodes and introduce a compact model with a new thermal equivalent circuit fitting data in the entire CDM to HBM timeframe. Further, we compare diode area efficiency in a full ESD protection ne...

Full description

Saved in:
Bibliographic Details
Published in:2006 Electrical Overstress/Electrostatic Discharge Symposium pp. 46 - 53
Main Authors: Stockinger, M., Miller, J.W.
Format: Conference Proceeding
Language:English
Published: IEEE 01-09-2006
Subjects:
CMOS technology
Electrical resistance measurement
Electrostatic discharge
Equivalent circuits
Measurement techniques
Network-on-a-chip
Protection
Pulse measurements
Semiconductor device modeling
Semiconductor diodes
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:We present advanced TLP measurement techniques down to 1.2ns pulses. We compare gated, STI and abutted tie diodes and introduce a compact model with a new thermal equivalent circuit fitting data in the entire CDM to HBM timeframe. Further, we compare diode area efficiency in a full ESD protection network.
ISSN:2164-9340
DOI:10.1109/EOSESD.2006.5256802