A 5 GHz Digitally Controlled Synthesizer in 90 nm CMOS

• Published in: 2009 IEEE Workshop on Microelectronics and Electron Devices pp. 1 - 4
• Main Authors: Hamon, B.J., Mandhanya, S., La Rue, G.S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-04-2009
• Subjects: Clocks; CMOS process; Delay; Digital control; Distributed control; Energy consumption; Frequency conversion; Frequency synthesizers; Jitter; Tuning
• ISBN: 142443551X; 9781424435517
• ISSN: 1947-3834; 1947-3842
• DOI: 10.1109/WMED.2009.4816155

A digitally controlled synthesizer (DCS) using a delay accumulator and a frequency divider is presented. The system operates with an output tuning range of 2.44 MHz to 2.5 GHz using a 5 GHz reference clock with a power consumption of 125 mW. It is designed in the IBM 90 nm CMOS process. The mostly digital design has no jitter accumulation, high tolerance to device and process variations, and a small form factor. The novel delay accumulator prevents the need of propagating carries reducing power dissipation and area. The design is tolerant to total ionizing dose radiation and single-event upsets.