FPGA Implementation of 160- Bit Vedic Multiplier

• Published in: 2014 International Conference on Devices, Circuits and Communications (ICDCCom) pp. 1 - 5
• Main Authors: Kodali, Ravi Kishore, Yenamachintala, Sai Sourabh, Boppana, Lakshmi
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-09-2014
• Subjects: Adders; Algorithm design and analysis; Computers; Delay effects; Field programmable gate arrays; Signal processing algorithms
• DOI: 10.1109/ICDCCom.2014.7024721

The rapid growth of technology influenced the need for the design of highly efficient digital systems. Multipliers have been playing a crucial role in every digital design. It is necessary to make use of an efficient multiplier. Many algorithms came into existence aiming at the reduction of execution time and area. Taking us back to the Vedic (ancient Indian) era, the sutras or algorithms described in Vedic mathematics rendered high degree of efficiency. Vedic mathematics describes 16 different sutras which involve multiplication operation. This work discusses one of the 16 sutras, urdhva tiryakbhyam sutra for multiplication. Two other multiplication algorithms namely, Booth and Karatsuba have been considered for the purpose of performance comparison. Elliptic Curve Cryptographic applications require repeated application of higher key size multiplication operation. All the three algorithms have been implemented using Xilinx FPGA and a resource utilization and timing summary comparison has been made.