High-level test generation for processing elements in many-core systems

• Published in: 2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) pp. 1 - 8
• Main Authors: Oyeniran, Adeboye Stephen, Ubar, Raimund, Azad, Siavoosh Payandeh, Raik, Jaan
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-07-2017
• Subjects: Built-in self-test; Circuit faults; Computer architecture; fault redundancy; high-level control faults; high-level fault coverage; Logic gates; processor core testing; Redundancy; test generation
• DOI: 10.1109/ReCoSoC.2017.8016156

The advent of many-core system-on-chips (SoC) will involve new scalable hardware/software mechanisms that can efficiently utilize the abundance of interconnected processing elements found in these SoCs. These trends will have a great impact on the strategies for testing the systems and improving their reliability by exploiting system's re-configurability to achieve graceful degradation of system's performance. We propose a strategy of Software-Based Self-Test (SBST) to be used for testing of processing elements in many-core systems with the goal to increase fault coverage and structuring the test routines in a way which makes test-data delivery in many-core systems more efficient. A new high-level fault model is introduced, which covers a broad class of gate-level Stuck-at-Faults (SAF), conditional SAF, and bridging faults of any multiplicity in processor control paths. Two algorithms for high-level simulation-based test generation for the control path and a bit-wise pseudo-exhaustive test approach for data path are proposed. No implementation details are needed for test data generation. A novel method for proving the redundancy of high-level functional faults is presented, which allows for precise evaluation of fault coverage.