100Gbit/s FEC for OTN protocol: Design architecture and implementation results

Error correcting codes are widely used in telecommunication systems in order to increase the robustness of the system. With the exponential growth of the data communication world, the architecture of such systems have had to adapt to allow for improved channel capacity and reduced transmission costs...

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Bibliographic Details
Published in:	2014 International Telecommunications Symposium (ITS) pp. 1 - 5
Main Authors:	Salvador, Arley, Carvalho, Diego, Nakandakare, Cleber, Mobilon, Eduardo, de Oliveira, Julio C., Arantes, Dalton S.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01-08-2014
Subjects:	100 Gbit/s Clocks Computer architecture Decoding FEC Field programmable gate arrays Forward error correction OTN Polynomials Reed Solomon Reed-Solomon codes
Online Access:	Get full text
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Summary:	Error correcting codes are widely used in telecommunication systems in order to increase the robustness of the system. With the exponential growth of the data communication world, the architecture of such systems have had to adapt to allow for improved channel capacity and reduced transmission costs. The architecture and hardware implementation challenges of the Reed Solomon RS(255, 239) for OTN networks in 100Gbit/s is presented.
DOI:	10.1109/ITS.2014.6947951