Low-voltage low-power CMOS design

Low-voltage low-power CMOS design

Minimal power dissipation is one of the main characteristics of portable devices, smart sensor networks and nodes, medical equipments, etc. The best choice is the sub threshold CMOS regime, where supply voltage is lower than threshold voltage of MOS transistor. In this paper it is shown that in sub...

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Bibliographic Details
Published in:2016 International Symposium on Industrial Electronics (INDEL) pp. 1 - 6
Main Authors: Dokic, Branko L., Pesic-Brdanin, Tatjana, Cavka, Drago
Format: Conference Proceeding
Language:English
Published: IEEE 01-11-2016
Subjects:
CMOS technology
full adder
Inverters
Logic gates
low-power
Low-voltage
MOSFET
Power dissipation
sub0020threshold
Threshold voltage
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Summary:Minimal power dissipation is one of the main characteristics of portable devices, smart sensor networks and nodes, medical equipments, etc. The best choice is the sub threshold CMOS regime, where supply voltage is lower than threshold voltage of MOS transistor. In this paper it is shown that in sub threshold CMOS regime, dissipation is influenced by transistor threshold voltage, beside supply voltage and CMOS technology parameters. It is shown that by decreasing threshold voltage the total dissipation increases. An energy efficient design means multiple-threshold CMOS. The analytic model of CMOS inverter dissipation is confirmed with simulations of 1-bit adder in P Spice, with implementation of 90 nm CMOS technology parameters.
DOI:10.1109/INDEL.2016.7797813