Design and analysis of a 7-level cascaded multilevel inverter with dual SDCSs

• Published in: SPEEDAM 2010 pp. 180 - 185
• Main Authors: Colak, I, Bayindir, R, Kabalci, E
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-06-2010
• Subjects: Employee welfare; Harmonic analysis; Insulated gate bipolar transistors; Leg; Phase modulation; Pulse width modulation; Pulse width modulation inverters; Space vector pulse width modulation; Topology; Voltage
• ISBN: 1424449863; 9781424449866
• DOI: 10.1109/SPEEDAM.2010.5542028

Multilevel inverters with a large number of steps can generate high quality voltage waveforms, good enough to be considered as suitable voltage source generators. A modified Sinusoidal Pulse Width Modulation (SPWM) modulator with phase disposition that increases output waveform up to 7-level while reducing output harmonics is presented in this paper. The proposed modulation technique can easily be applied to any multilevel inverter topology carrying out the necessary calculations. The modulator block is designed to control multilevel inverter that is constituted using dual H-bridge cells with IGBTs on each phase legs. The supply voltages of cells are defined at V dc ÷2V dc ratio to obtain an asymmetrical output. The output waveform of asymmetrical topology is increased up to 7-level by using dual separate DC sources (SDCSs). The DC supply requirement of asymmetrical cascaded topology is solved using dual sources instead of 6 SDCSs. The cascaded multilevel inverter is switched by the proposed 24-channel SPWM modulator. The harmonic analysis of proposed inverter has been performed under several working conditions such as various switching frequencies and modulation indexes. The detailed comparisons are performed to determine the best working conditions of voltage source inverters (VSI) and presented in this paper.