Investigating degradation mechanisms in 130 nm and 90 nm commercial CMOS technologies exposed to up to 100 Mrad ionizing radiation dose

• Published in: 2007 9th European Conference on Radiation and Its Effects on Components and Systems pp. 1 - 9
• Main Authors: Ratti, L., Gaioni, L., Manghisoni, M., Traversi, G., Pantano, D.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-09-2007
• Subjects: Analog circuits; Circuit noise; CMOS technology; deep submicron CMOS; Degradation; flicker noise; Ionizing radiation; Isolation technology; MOSFETs; Semiconductor device modeling; thermal noise; Working environment noise; X-rays
• ISBN: 9781424417049; 142441704X
• ISSN: 0379-6566
• DOI: 10.1109/RADECS.2007.5205526

The purpose of this paper is to study the mechanisms underlying performance degradation in 130 nm and 90 nm commercial CMOS technologies exposed to high doses of ionizing radiation. The investigation has been mainly focused on their noise properties in view of applications to the design of low-noise, low-power analog circuits to be operated in harsh environment. Experimental data support the hypothesis that charge trapping in shallow trench isolation (STI), besides degrading the static characteristics of interdigitated NMOS transistors, also affects their noise performances in a substantial fashion. The model discussed in this paper, presented in a previous work focused on CMOS devices irradiated with a 10 Mrad(SiO 2 ) gamma-ray dose, has been applied here also to transistors exposed to much higher (up to 100 Mrad(SiO 2 )) doses of X-rays. Such a model is able to account for the extent of the observed noise degradation as a function of the device polarity, dimensions and operating point.