Analysis of Standard Cells performance for In0.53Ga0.47As FinFET with underlap fin length for High Speed Applications

• Published in: 2021 25th International Symposium on VLSI Design and Test (VDAT) pp. 1 - 4
• Main Authors: Pathak, Jay, Darji, Anand
• Format: Conference Proceeding
• Language: English
• Published: IEEE 16-09-2021
• Subjects: CMOS technology; Digital systems; FinFETs; In 0.53 Ga 0.47 As FinFET; Logic gates; Performance evaluation; Process Variation and Delay; Simulation; Standard Cells; Underlap Fin Length; Very large scale integration
• DOI: 10.1109/VDAT53777.2021.9600972

In current CMOS technology for high-speed applications at the sub-14 nm technology node using In 0.53 Ga 0.47 As FinFETs is becoming a promising choice because of its exceptional electrical properties. The approach of improving FinFET standard cells utilizing In 0.53 Ga 0.47 As nFinFETs is suggested to offer a platform in advanced VLSI digital system flow occupying various standard cells. Gate-source/drain (G-S/D) underlap fin length (L un ) structures are effectively used to reduce the short channel effects for a long time. In this work, the implementation of various standard cells with different L un in In 0.53 Ga 0.47 As nFinFETs to understand its significance. The device reliability was tested in the proposed work by varying the process variation on the height of fin, gate oxide thickness, and channel length offset parameter. Simulation results performed on the different standard cells with L un = 3 nm method indicate the minimum delay by 42.26%.