Null convention logic (NCL) based asynchronous design - fundamentals and recent advances

Null convention logic (NCL) based asynchronous design - fundamentals and recent advances

As clock skew and power consumption become major challenges in deep submicron design of synchronous circuits, asynchronous designs, especially Null Convention Logic (NCL) subset, is gaining more and more attention. The NCL methodology eliminates problems related to the clock tree and also, can signi...

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Bibliographic Details
Published in:2017 International Conference on Recent Advances in Signal Processing, Telecommunications & Computing (SigTelCom) pp. 158 - 163
Main Authors: Linh Duc Tran, Matthews, Glenn I., Beckett, Paul, Stojcevski, Alex
Format: Conference Proceeding
Language:English
Published: IEEE 01-01-2017
Subjects:
Asynchronous circuits
asynchronous design
Delays
Encoding
Hysteresis
Logic gates
Null Convention Logic (NCL)
Quasi-delay-insensitive (QDI)
Registers
Wires
Online Access:Get full text
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Summary:As clock skew and power consumption become major challenges in deep submicron design of synchronous circuits, asynchronous designs, especially Null Convention Logic (NCL) subset, is gaining more and more attention. The NCL methodology eliminates problems related to the clock tree and also, can significantly reduce power consumption, noise and electromagnetic interference (EMI). In this paper, we present a comprehensive introduction to the NCL design approach, from fundamentals to recent advances. In addition, automated design flows for NCL circuits are also discussed.
DOI:10.1109/SIGTELCOM.2017.7849815