FPGA based delay PUF implementation for security applications

• Published in: 2017 International Conference on Technological Advancements in Power and Energy ( TAP Energy) pp. 1 - 6
• Main Authors: Kumar, Mahin Anil, Bhakthavatchalu, Ramesh
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-12-2017
• Subjects: Arbiter; CRPs; Delays; Feed Forward; Feeds; Field programmable gate arrays; FPGA; Hardware design languages; Integrated circuit modeling; Lightweight; Reliability; Security
• DOI: 10.1109/TAPENERGY.2017.8397339

A new type of authentication of a device or chip called Physically Unclonable functions (PUFs) is developed such that, with the built-in manufacturing differences, it provides security. A delay based Physical Unclonable Function (PUF) is implemented in this project on FPGA and its presentation is experimented. By using combinatorial logic, the PUF logic execution is done. In this project, four types of delay PUFs, viz, Arbiter PUF, Xor - Arbiter PUF, Lightweight Secure PUF and Feed Forward PUF are implemented. Delay based PUF utilize built-in delay characteristics of the physical components that alters between chip to chip. Low-cost validation of IC's based on PUFs usage is described. The CRP's usage are for the authentication of a chip or a gadget. The entire project is implemented using Verilog HDL and synthesised with a Xilinx Vivado 2012.2. This project focuses on reducing area consumption, increasing speed and consuming low power.