Highly Optimized Nanocrystal-Based Split Gate Flash for High Performance and Low Power Microcontroller Applications

• Published in: 2011 3rd IEEE International Memory Workshop (IMW) pp. 1 - 4
• Main Authors: Yater, J, Hong, C, Kang, S.-T, Kolar, D, Min, B, Shen, J, Chindalore, G, Loiko, K, Winstead, B, Williams, S, Gasquet, H, Suhail, M, Broeker, K, Lepore, E, Hardell, A, Malloch, W, Syzdek, R, Chen, Y, Ju, Y, Kumarasamy, S, Liu, H, Lei, L, Indajang, B
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-05-2011
• Subjects: Acceleration; Arrays; Logic gates; Microcontrollers; Nanocrystals; Programming; Reliability
• ISBN: 1457702258; 9781457702259
• ISSN: 2159-483X
• DOI: 10.1109/IMW.2011.5873213

We show a 90nm nanocrystal-based split gate embedded flash memory that is able to meet the speed, endurance and reliability requirements for 32-bit microcontroller products. A 3.4V operating window is achievable and the process is robust and repeatable across many lots. Erase after 10k cycles can be achieved in 5ms, long-term data retention of cycled arrays is not susceptible to SILC-induced charge loss mechanisms, and program disturb can meet the needs of flash and EEPROM.