Development of Junction Temperature Decision (JTD) Map for Thermal Design of Nano-scale Devices Considering Leakage Power

• Published in: Twenty-Third Annual IEEE Semiconductor Thermal Measurement and Management Symposium pp. 63 - 67
• Main Authors: Yunhyeok Im, Eun Seok Cho, Kiwon Choi, Sayoon Kang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-03-2007
• Subjects: CJT Curve; Electronic packaging thermal management; ITL Map; JTD Map; Leakage Power; Mechanical engineering; Nano-scale Devices; Nanoscale devices; Power system reliability; Process design; Temperature distribution; Thermal engineering; Thermal resistance; Threshold voltage; Very large scale integration
• ISBN: 1424409586; 9781424409587
• ISSN: 1065-2221
• DOI: 10.1109/STHERM.2007.352407

As semiconductor technology keeps scaling down, leakage power grows significantly due to the reduction in threshold voltage, channel length, and gate oxide thickness. As the junction temperature increases in nano-scale devices, leakage power increases drastically. This phenomenon motivates the processor and package designers to take into account thermal effects due to the large leakage power for highly reliable design of high-performance systems. In this paper, an analytical methodology for estimating the junction temperature and initial temperature range was provided to avoid diverging junction temperature status in nano-scale devices. For this purpose, junction temperature decision (JTD) map and initial temperature limit (ITL) map was newly introduced.