Silicon film thickness influence on enhanced dynamic threshold UTBB SOI nMOSFETs

• Published in: 2014 29th Symposium on Microelectronics Technology and Devices (SBMicro) pp. 1 - 4
• Main Authors: Sasaki, Katia R. A., Aoulaiche, Marc, Simoen, Eddy, Claeys, Cor, Martino, Joao A.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-09-2014
• Subjects: Couplings; DTMOS; Junctions; Lead; Logic gates; silicon film thickness; UTBB
• DOI: 10.1109/SBMicro.2014.6940089

This paper investigates the silicon film thickness influence on extensionless Ultra Thin Body and Buried Oxide (UTBB) FDSOI devices applied in a dynamic threshold voltage (DT2) operation (V B =V G ) over the conventional one (V B =0V). A 6nm silicon thickness in enhanced DT (eDT), where the back gate bias is a multiple value of the front gate one (V B =k×V G ), was also considered and compared to the other configurations and to a 14nm silicon film. The better coupling of a thinner silicon film leads to superior DC parameters like lower subthreshold swing and DIBL, while the thicker device presents a higher gm max and lower GIDL. Regarding the eDT performance, the parameters of the thinner channel vary less than for the thicker one.