An ultra-fast, on-chip BiST for RF low noise amplifiers

• Published in: 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design pp. 485 - 490
• Main Authors: Gopalan, A., Das, T., Washburn, C., Mukund, P.R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2005
• Subjects: Automatic testing; Built-in self-test; Circuit noise; Circuit testing; Digital signal processing; Impedance matching; Linearity; Low-noise amplifiers; Radio frequency; Radiofrequency amplifiers
• ISBN: 0769522645; 9780769522647
• ISSN: 1063-9667; 2380-6923
• DOI: 10.1109/ICVD.2005.52

This paper presents an ultra-fast built in self test (BiST) approach for RF low noise amplifiers. The technique uses test inputs of moderate precision and low overhead base-band circuitry to quantify various functional specifications in the LNA such as input/output match, power gain and linearity. The total self-test time for all these parameters is 15/spl mu/s, which is several orders of magnitude improvement over existing test techniques. The BiST circuitry described presents low real estate and power overheads and does not require the presence of DSP cores to achieve self-test. The technique has been demonstrated for a 1.9GHz cascode LNA designed in the 0.25 micron IBM 6RF process.