Strained In0.53Ga0.47As n-MOSFETs: Performance boost with in-situ doped lattice-mismatched source/drain stressors and interface engineering
We report the first demonstration of strained III-V n-MOSFETs with lattice-mismatched source/drain (S/D) stressors. Lateral tensile strain was induced by In 0.4 Ga 0.6 As S/D on the In 0.53 Ga 0.47 As channel. In-situ doping was incorporated as well for series resistance reduction. We also integrate...
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Published in: | 2009 Symposium on VLSI Technology pp. 244 - 245 |
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01-06-2009
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Abstract | We report the first demonstration of strained III-V n-MOSFETs with lattice-mismatched source/drain (S/D) stressors. Lateral tensile strain was induced by In 0.4 Ga 0.6 As S/D on the In 0.53 Ga 0.47 As channel. In-situ doping was incorporated as well for series resistance reduction. We also integrated SiH 4 +NH 3 passivation for reduction of interface state density on In 0.53 Ga 0.47 As for the first time. |
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AbstractList | We report the first demonstration of strained III-V n-MOSFETs with lattice-mismatched source/drain (S/D) stressors. Lateral tensile strain was induced by In 0.4 Ga 0.6 As S/D on the In 0.53 Ga 0.47 As channel. In-situ doping was incorporated as well for series resistance reduction. We also integrated SiH 4 +NH 3 passivation for reduction of interface state density on In 0.53 Ga 0.47 As for the first time. |
Author | Hock-Chun Chin Xinke Liu Yee-Chia Yeo Xiao Gong Zhe Lin |
Author_xml | – sequence: 1 surname: Hock-Chun Chin fullname: Hock-Chun Chin organization: Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore(NUS), Singapore, Singapore – sequence: 2 surname: Xiao Gong fullname: Xiao Gong organization: Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore(NUS), Singapore, Singapore – sequence: 3 surname: Xinke Liu fullname: Xinke Liu organization: Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore(NUS), Singapore, Singapore – sequence: 4 surname: Zhe Lin fullname: Zhe Lin organization: Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore(NUS), Singapore, Singapore – sequence: 5 surname: Yee-Chia Yeo fullname: Yee-Chia Yeo organization: Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore(NUS), Singapore, Singapore |
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Snippet | We report the first demonstration of strained III-V n-MOSFETs with lattice-mismatched source/drain (S/D) stressors. Lateral tensile strain was induced by In... |
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SubjectTerms | Annealing Capacitive sensors Dielectric substrates Doping Epitaxial growth Fabrication III-V semiconductor materials MOSFET circuits Passivation Tensile strain |
Title | Strained In0.53Ga0.47As n-MOSFETs: Performance boost with in-situ doped lattice-mismatched source/drain stressors and interface engineering |
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