An FFT core for DVB-T2 receivers

An FFT core for DVB-T2 receivers

This paper presents the design and implementation of a pipeline radix-2 5 SDF FFT core for DVB-T2 receivers. DVB-T2 operation needs 1K/2K/4K/8K/16K/32K multiple mode FFT processors. The radix-2 5 SDF architecture is a new and more efficient architecture, which has been optimized for implementing a m...

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Bibliographic Details
Published in:2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009) pp. 120 - 123
Main Authors: Turrillas, M., Cortes, A., Velez, I., Sevillano, J.F., Irizar, A.
Format: Conference Proceeding
Language:English
Published: IEEE 01-12-2009
Subjects:
Delay
Digital video broadcasting
Discrete Fourier transforms
Fast Fourier transforms
Flow graphs
HDTV
OFDM modulation
Pipelines
Throughput
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Summary:This paper presents the design and implementation of a pipeline radix-2 5 SDF FFT core for DVB-T2 receivers. DVB-T2 operation needs 1K/2K/4K/8K/16K/32K multiple mode FFT processors. The radix-2 5 SDF architecture is a new and more efficient architecture, which has been optimized for implementing a multiple mode core. SNR results for different data and twiddle factor bitwidths are provided. Furthermore, the results of the FFT core implementation in an FPGA are presented.
ISBN:9781424450909
142445090X
DOI:10.1109/ICECS.2009.5410934