Dynamic logic styles with improved noise-immunity

• Published in: Proceedings of the Fourth IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.02TH8611) p. C031
• Main Authors: Mendoza-Hernandez, F., Linarea, M., Champac, V.H.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2002
• Subjects: Circuit noise; CMOS logic circuits; Delay effects; Digital systems; Energy consumption; Integrated circuit interconnections; Logic circuits; Logic devices; Power system interconnection; Very large scale integration
• ISBN: 0780373804; 9780780373808
• DOI: 10.1109/ICCDCS.2002.1004019

Noise issues are becoming an important concern in digital systems due to the aggressive scaling trends in devices and interconnections. Noise effects in deep submicron CMOS VLSI circuits have an importance comparable to area, delay and power consumption. To address this problem a new noise-tolerant dynamic circuit technique suitable for dynamic logic styles is presented. Simulation results show that the proposed technique improves the ANTE (Balamurugan and Shanbhag, IEEE J. Solid-State Circ., vol. 36, no. 2, pp. 273-280, 2001) by 3.4/spl times/ and 2.8/spl times/ over conventional dynamic true single-phase-clock (TSPC) and Domino logic, respectively. The improvement in the ANTE-delay quotient is 2.8/spl times/ and 2.25/spl times/ over conventional dynamic logic, 2.0/spl times/ and 1.7/spl times/ over twin-transistor technique, 1.7/spl times/ and 1.04/spl times/ over Bobba's technique for CMOS TSPC and Domino AND gates, respectively.