Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor

• Published in: International Symposium on Low Power Electronics and Design (ISLPED) pp. 193 - 198
• Main Authors: Drake, Alan J., Floyd, Michael S., Willaman, Richard L., Hathaway, Derek J., Hernandez, Joshua, Soja, Crystal, Tiner, Marshall D., Carpenter, Gary D., Senger, Robert M.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01-09-2013
• Subjects: Calibration; Critical Path Monitor; Delays; Detectors; DVFS; Image edge detection; Latches; process variation; Wires
• DOI: 10.1109/ISLPED.2013.6629293

A 32nm SOI critical path monitor (CPM) that can provide timing measurements to a Digital PLL for dynamic frequency adjustments in the 8-core POWER7+™ microprocessor is described. The CPM calibrates to within 2% of cycle time from nominal to turbo voltages. Its voltage sensitivity is 10mV/bit. It tracks processor temperature sensitivity to within 1.5% of nominal frequency, and has a sample jitter less than 1.5% of nominal frequency. The ability to detect noise dynamically allows the system to operate the processor closer to its optimal frequency for any given voltage, resulting in lower voltage for power savings or higher frequency for performance improvements.