Subthreshold leakage power reduction in VLSI circuits: A survey

Subthreshold leakage power reduction in VLSI circuits: A survey

As technology enters into deep submicron regime, subthreshold leakage power increases exponentially and become a limiting factor in the performance of portable and battery operated electronic devices. To increase the life of battery and computational capacities of portable devices the reduction of p...

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Bibliographic Details
Published in:2016 International Conference on Communication and Signal Processing (ICCSP) pp. 1120 - 1124
Main Authors: Sridhara, K., Biradar, G. S., Yanamshetti, Raju
Format: Conference Proceeding
Language:English
Published: IEEE 01-04-2016
Subjects:
Delays
Leakage currents
Leakage power
LECTOR
Logic gates
MOSFET
MTCMOS
PDN
Power gating
Sleepy keeper
Subthreshold current
subthreshold leakage power PUN
Subthreshold source coupled logic
Super cut-off CMOS
Switching circuits
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Summary:As technology enters into deep submicron regime, subthreshold leakage power increases exponentially and become a limiting factor in the performance of portable and battery operated electronic devices. To increase the life of battery and computational capacities of portable devices the reduction of power in standby/ sleep mode is evident. Now a day's power dissipation emerged as a major design constraint in the device miniaturization and integration of huge number of transistors. A detailed survey of alternative techniques to reduce subthreshold leakage power is presented in this paper.
DOI:10.1109/ICCSP.2016.7754326